Every electronic device (for example, a circuit integrated in a chip of semiconductor material or a package embedding one or more chips) is provided with multiple electrical contacts; those contacts consist of points at which electrical connections are made to implement any Input/Output (I/O) function of the electronic device.
For example, the electrical contacts of a chip may be in the form of pads (i.e., flat elements generally with rectangular or square shape) or bumps (i.e., non-planar elements generally with a spherical, semi-spherical, ellipsoidal, or cylindrical shape); the bumps can also be mounted on a micro-spring so as to obtain a resilient structure (known as compliant bump). When the chip is embedded in a package, the pads or bumps are connected to corresponding electrical contacts of the package. Typically, the pads of the chip are connected to a lead frame or a circuitized substrate of the package by means of wires (with a technique known as wire-bonding); conversely, the bumps of the chip are directly connected to the substrate of the package (with a technique known as flip-chip). On the other hand, the electrical contacts of the package may be in the form of pins (i.e., slander elements projecting laterally from a body of the package), or bumps (which are formed on an exposed surface of its substrate and are connected to the chip mounted on an opposed surface thereof by means of corresponding vias). For example, the pins can be of the gull-wing type, of the J type, and the like; instead, the packages based on the bumps can be of the Ball Grid Array, or BGA, type (when the chip is wire-bonded to pads of the substrate), or of the Chip Scale Package, or CSP, (when the chip is mounted with the flip-chip technique onto the substrate). Those electrical contacts are typically used to mount the package on a Printed Circuit Board (PCB); the operation can be performed either with a standard technique (in which the pins are welded into corresponding holes of the board) or with the Surface Mounting Technology, or SMT; in the latest case, the electrical contacts of the package are slightly pressed (with a process known as pick-and-place) onto corresponding pads of the board provided with a solder past, and then heated to cause the reflow of the solder past.
Several solutions are available in the art for contacting the electronic devices in a number of applications.
A specific example is the test of the electronic devices, which is used to verify their correct operation. The test can be aimed at either identifying evident defects or potential defects (which could occur after a short life of the electronic device). In the last case, the electronic devices are tested under stress conditions; a typical example is the so called burn-in test, which consists of making the electronic devices work for tens of hours at very high or very low temperature (such as ranging from −50° C. to +150° C.), in order to simulate a long period of operation of the electronic devices at room temperature (25° C.-50° C.). When the electronic devices are tested at the wafer level, the chips are contacted by means of a probe card; this card is provided with multiple probes, each one for contacting a corresponding pad or bump of the chips. On the other hand, when the electronic devices are tested at the package level, they are mounted on sockets of a Bum-In Board (BIB); the sockets have a structure that is similar to the one of the probe cards (or even simpler). In both cases, the probes must have a compliant structure, so as to contact the electronic devices under test correctly (especially at the wafer level).
A solution known in the art for implementing the above-described probes is of using cantilever blades. Another proposed technique is based on the use of micro-springs. Moreover, some available structures exploit a flexible membrane for the probes.
However, the available solutions may not be completely satisfactory in some applications. For example, some probes (such as the cantilever ones) are ineffective in accessing multiple electrical contacts of the electronic devices. Moreover, the proposed structures often require the application of a relatively high force to cause their elastic yield. When the probes must work at Radio Frequency (RF), the membrane architecture is generally required. However, in this case the probes are not resilient at an individual level; besides, these probes are unable to scrub (or penetrate) a native oxide layer (which naturally forms on the pads). In any case, all the probes known in the art damage the bumps; therefore, the bumps must be reflowed after the test to restore their original shape.
Another example is the assembling of power chips (i.e., working at a power higher than a hundred of watts). Currently, the integration of power components in a single chip is not feasible (for either technical or economical reasons). Therefore, the power components of each electronic device (such as diodes, MOS transistors, and IGBTs) are individually integrated into corresponding chips, which are mounted onto a common circuitized substrate; the power chips are then connected to conductive tracks of the substrate with the wire-bonding technique. This technique allows compensating the difference in level between the pads of the power chips and the conductive tracks. The driving circuits for the power chips are instead mounted on a distinct circuitized substrate using the SMT technique (which provides a higher integration). The two substrates (with the power chips and the driving circuits) are then embedded into a single package.
However, this solution strongly hinders the implementation of electronic devices with low electromagnetic emission. Moreover, the heat dissipation of the power chips is not optimized (since it can occur through the substrate only). The above-described solution also limits the performance of the electronic devices in terms of their working frequency.
A similar structure is also used to make packages including generic multiple chips (either of the power type or not), commonly referred to as multi-chip modules. Even in this case, the chips are mounted onto a common circuitized substrate and are wire-bonded to each other (with the structure so obtained that is then embedded into a package). Therefore, the solution known in the art suffers the same drawbacks mentioned above with reference to the wire-bonding technique.